\doxysubsubsection{Nested Vectored Interrupt Controller (NVIC) }
\hypertarget{group___c_m_s_i_s___n_v_i_c}{}\label{group___c_m_s_i_s___n_v_i_c}\index{Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}}


Type definitions for the NVIC Registers.  


\doxysubsubsubsubsection*{Topics}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{group___c_m_s_i_s___s_c_b}{System Control Block (\+SCB)}}
\begin{DoxyCompactList}\small\item\em Type definitions for the System Control Block Registers. \end{DoxyCompactList}\end{DoxyCompactItemize}
\doxysubsubsubsubsection*{Classes}
\begin{DoxyCompactItemize}
\item 
struct \mbox{\hyperlink{struct_n_v_i_c___type}{NVIC\+\_\+\+Type}}
\begin{DoxyCompactList}\small\item\em Structure type to access the Nested Vectored Interrupt Controller (NVIC). \end{DoxyCompactList}\end{DoxyCompactItemize}
\begin{DoxyCompactItemize}
\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos}}~0U
\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gae4060c4dfcebb08871ca4244176ce752}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Msk}}~(0x1\+FFUL /\texorpdfstring{$\ast$}{*}$<$$<$ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos}}\texorpdfstring{$\ast$}{*}/)
\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos}}~0U
\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gae4060c4dfcebb08871ca4244176ce752}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Msk}}~(0x1\+FFUL /\texorpdfstring{$\ast$}{*}$<$$<$ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos}}\texorpdfstring{$\ast$}{*}/)
\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos}}~0U
\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gae4060c4dfcebb08871ca4244176ce752}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Msk}}~(0x1\+FFUL /\texorpdfstring{$\ast$}{*}$<$$<$ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos}}\texorpdfstring{$\ast$}{*}/)
\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos}}~0U
\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gae4060c4dfcebb08871ca4244176ce752}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Msk}}~(0x1\+FFUL /\texorpdfstring{$\ast$}{*}$<$$<$ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos}}\texorpdfstring{$\ast$}{*}/)
\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos}}~0U
\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gae4060c4dfcebb08871ca4244176ce752}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Msk}}~(0x1\+FFUL /\texorpdfstring{$\ast$}{*}$<$$<$ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos}}\texorpdfstring{$\ast$}{*}/)
\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos}}~0U
\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gae4060c4dfcebb08871ca4244176ce752}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Msk}}~(0x1\+FFUL /\texorpdfstring{$\ast$}{*}$<$$<$ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos}}\texorpdfstring{$\ast$}{*}/)
\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos}}~0U
\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gae4060c4dfcebb08871ca4244176ce752}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Msk}}~(0x1\+FFUL /\texorpdfstring{$\ast$}{*}$<$$<$ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos}}\texorpdfstring{$\ast$}{*}/)
\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos}}~0U
\item 
\#define \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gae4060c4dfcebb08871ca4244176ce752}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Msk}}~(0x1\+FFUL /\texorpdfstring{$\ast$}{*}$<$$<$ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos}}\texorpdfstring{$\ast$}{*}/)
\end{DoxyCompactItemize}


\doxysubsubsubsection{Detailed Description}
Type definitions for the NVIC Registers. 



\label{doc-define-members}
\Hypertarget{group___c_m_s_i_s___n_v_i_c_doc-define-members}
\doxysubsubsubsection{Macro Definition Documentation}
\Hypertarget{group___c_m_s_i_s___c_o_r_e_gae4060c4dfcebb08871ca4244176ce752}\index{Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}!NVIC\_STIR\_INTID\_Msk@{NVIC\_STIR\_INTID\_Msk}}
\index{NVIC\_STIR\_INTID\_Msk@{NVIC\_STIR\_INTID\_Msk}!Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}}
\doxysubsubsubsubsection{\texorpdfstring{NVIC\_STIR\_INTID\_Msk}{NVIC\_STIR\_INTID\_Msk}\hspace{0.1cm}{\footnotesize\ttfamily [1/8]}}
{\footnotesize\ttfamily \label{group___c_m_s_i_s___c_o_r_e_gae4060c4dfcebb08871ca4244176ce752} 
\#define NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Msk~(0x1\+FFUL /\texorpdfstring{$\ast$}{*}$<$$<$ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos}}\texorpdfstring{$\ast$}{*}/)}

STIR\+: INTLINESNUM Mask \Hypertarget{group___c_m_s_i_s___c_o_r_e_gae4060c4dfcebb08871ca4244176ce752}\index{Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}!NVIC\_STIR\_INTID\_Msk@{NVIC\_STIR\_INTID\_Msk}}
\index{NVIC\_STIR\_INTID\_Msk@{NVIC\_STIR\_INTID\_Msk}!Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}}
\doxysubsubsubsubsection{\texorpdfstring{NVIC\_STIR\_INTID\_Msk}{NVIC\_STIR\_INTID\_Msk}\hspace{0.1cm}{\footnotesize\ttfamily [2/8]}}
{\footnotesize\ttfamily \label{group___c_m_s_i_s___c_o_r_e_gae4060c4dfcebb08871ca4244176ce752} 
\#define NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Msk~(0x1\+FFUL /\texorpdfstring{$\ast$}{*}$<$$<$ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos}}\texorpdfstring{$\ast$}{*}/)}

STIR\+: INTLINESNUM Mask \Hypertarget{group___c_m_s_i_s___c_o_r_e_gae4060c4dfcebb08871ca4244176ce752}\index{Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}!NVIC\_STIR\_INTID\_Msk@{NVIC\_STIR\_INTID\_Msk}}
\index{NVIC\_STIR\_INTID\_Msk@{NVIC\_STIR\_INTID\_Msk}!Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}}
\doxysubsubsubsubsection{\texorpdfstring{NVIC\_STIR\_INTID\_Msk}{NVIC\_STIR\_INTID\_Msk}\hspace{0.1cm}{\footnotesize\ttfamily [3/8]}}
{\footnotesize\ttfamily \label{group___c_m_s_i_s___c_o_r_e_gae4060c4dfcebb08871ca4244176ce752} 
\#define NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Msk~(0x1\+FFUL /\texorpdfstring{$\ast$}{*}$<$$<$ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos}}\texorpdfstring{$\ast$}{*}/)}

STIR\+: INTLINESNUM Mask \Hypertarget{group___c_m_s_i_s___c_o_r_e_gae4060c4dfcebb08871ca4244176ce752}\index{Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}!NVIC\_STIR\_INTID\_Msk@{NVIC\_STIR\_INTID\_Msk}}
\index{NVIC\_STIR\_INTID\_Msk@{NVIC\_STIR\_INTID\_Msk}!Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}}
\doxysubsubsubsubsection{\texorpdfstring{NVIC\_STIR\_INTID\_Msk}{NVIC\_STIR\_INTID\_Msk}\hspace{0.1cm}{\footnotesize\ttfamily [4/8]}}
{\footnotesize\ttfamily \label{group___c_m_s_i_s___c_o_r_e_gae4060c4dfcebb08871ca4244176ce752} 
\#define NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Msk~(0x1\+FFUL /\texorpdfstring{$\ast$}{*}$<$$<$ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos}}\texorpdfstring{$\ast$}{*}/)}

STIR\+: INTLINESNUM Mask \Hypertarget{group___c_m_s_i_s___c_o_r_e_gae4060c4dfcebb08871ca4244176ce752}\index{Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}!NVIC\_STIR\_INTID\_Msk@{NVIC\_STIR\_INTID\_Msk}}
\index{NVIC\_STIR\_INTID\_Msk@{NVIC\_STIR\_INTID\_Msk}!Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}}
\doxysubsubsubsubsection{\texorpdfstring{NVIC\_STIR\_INTID\_Msk}{NVIC\_STIR\_INTID\_Msk}\hspace{0.1cm}{\footnotesize\ttfamily [5/8]}}
{\footnotesize\ttfamily \label{group___c_m_s_i_s___c_o_r_e_gae4060c4dfcebb08871ca4244176ce752} 
\#define NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Msk~(0x1\+FFUL /\texorpdfstring{$\ast$}{*}$<$$<$ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos}}\texorpdfstring{$\ast$}{*}/)}

STIR\+: INTLINESNUM Mask \Hypertarget{group___c_m_s_i_s___c_o_r_e_gae4060c4dfcebb08871ca4244176ce752}\index{Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}!NVIC\_STIR\_INTID\_Msk@{NVIC\_STIR\_INTID\_Msk}}
\index{NVIC\_STIR\_INTID\_Msk@{NVIC\_STIR\_INTID\_Msk}!Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}}
\doxysubsubsubsubsection{\texorpdfstring{NVIC\_STIR\_INTID\_Msk}{NVIC\_STIR\_INTID\_Msk}\hspace{0.1cm}{\footnotesize\ttfamily [6/8]}}
{\footnotesize\ttfamily \label{group___c_m_s_i_s___c_o_r_e_gae4060c4dfcebb08871ca4244176ce752} 
\#define NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Msk~(0x1\+FFUL /\texorpdfstring{$\ast$}{*}$<$$<$ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos}}\texorpdfstring{$\ast$}{*}/)}

STIR\+: INTLINESNUM Mask \Hypertarget{group___c_m_s_i_s___c_o_r_e_gae4060c4dfcebb08871ca4244176ce752}\index{Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}!NVIC\_STIR\_INTID\_Msk@{NVIC\_STIR\_INTID\_Msk}}
\index{NVIC\_STIR\_INTID\_Msk@{NVIC\_STIR\_INTID\_Msk}!Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}}
\doxysubsubsubsubsection{\texorpdfstring{NVIC\_STIR\_INTID\_Msk}{NVIC\_STIR\_INTID\_Msk}\hspace{0.1cm}{\footnotesize\ttfamily [7/8]}}
{\footnotesize\ttfamily \label{group___c_m_s_i_s___c_o_r_e_gae4060c4dfcebb08871ca4244176ce752} 
\#define NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Msk~(0x1\+FFUL /\texorpdfstring{$\ast$}{*}$<$$<$ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos}}\texorpdfstring{$\ast$}{*}/)}

STIR\+: INTLINESNUM Mask \Hypertarget{group___c_m_s_i_s___c_o_r_e_gae4060c4dfcebb08871ca4244176ce752}\index{Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}!NVIC\_STIR\_INTID\_Msk@{NVIC\_STIR\_INTID\_Msk}}
\index{NVIC\_STIR\_INTID\_Msk@{NVIC\_STIR\_INTID\_Msk}!Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}}
\doxysubsubsubsubsection{\texorpdfstring{NVIC\_STIR\_INTID\_Msk}{NVIC\_STIR\_INTID\_Msk}\hspace{0.1cm}{\footnotesize\ttfamily [8/8]}}
{\footnotesize\ttfamily \label{group___c_m_s_i_s___c_o_r_e_gae4060c4dfcebb08871ca4244176ce752} 
\#define NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Msk~(0x1\+FFUL /\texorpdfstring{$\ast$}{*}$<$$<$ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}{NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos}}\texorpdfstring{$\ast$}{*}/)}

STIR\+: INTLINESNUM Mask \Hypertarget{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}\index{Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}!NVIC\_STIR\_INTID\_Pos@{NVIC\_STIR\_INTID\_Pos}}
\index{NVIC\_STIR\_INTID\_Pos@{NVIC\_STIR\_INTID\_Pos}!Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}}
\doxysubsubsubsubsection{\texorpdfstring{NVIC\_STIR\_INTID\_Pos}{NVIC\_STIR\_INTID\_Pos}\hspace{0.1cm}{\footnotesize\ttfamily [1/8]}}
{\footnotesize\ttfamily \label{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8} 
\#define NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos~0U}

STIR\+: INTLINESNUM Position \Hypertarget{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}\index{Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}!NVIC\_STIR\_INTID\_Pos@{NVIC\_STIR\_INTID\_Pos}}
\index{NVIC\_STIR\_INTID\_Pos@{NVIC\_STIR\_INTID\_Pos}!Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}}
\doxysubsubsubsubsection{\texorpdfstring{NVIC\_STIR\_INTID\_Pos}{NVIC\_STIR\_INTID\_Pos}\hspace{0.1cm}{\footnotesize\ttfamily [2/8]}}
{\footnotesize\ttfamily \label{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8} 
\#define NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos~0U}

STIR\+: INTLINESNUM Position \Hypertarget{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}\index{Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}!NVIC\_STIR\_INTID\_Pos@{NVIC\_STIR\_INTID\_Pos}}
\index{NVIC\_STIR\_INTID\_Pos@{NVIC\_STIR\_INTID\_Pos}!Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}}
\doxysubsubsubsubsection{\texorpdfstring{NVIC\_STIR\_INTID\_Pos}{NVIC\_STIR\_INTID\_Pos}\hspace{0.1cm}{\footnotesize\ttfamily [3/8]}}
{\footnotesize\ttfamily \label{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8} 
\#define NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos~0U}

STIR\+: INTLINESNUM Position \Hypertarget{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}\index{Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}!NVIC\_STIR\_INTID\_Pos@{NVIC\_STIR\_INTID\_Pos}}
\index{NVIC\_STIR\_INTID\_Pos@{NVIC\_STIR\_INTID\_Pos}!Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}}
\doxysubsubsubsubsection{\texorpdfstring{NVIC\_STIR\_INTID\_Pos}{NVIC\_STIR\_INTID\_Pos}\hspace{0.1cm}{\footnotesize\ttfamily [4/8]}}
{\footnotesize\ttfamily \label{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8} 
\#define NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos~0U}

STIR\+: INTLINESNUM Position \Hypertarget{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}\index{Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}!NVIC\_STIR\_INTID\_Pos@{NVIC\_STIR\_INTID\_Pos}}
\index{NVIC\_STIR\_INTID\_Pos@{NVIC\_STIR\_INTID\_Pos}!Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}}
\doxysubsubsubsubsection{\texorpdfstring{NVIC\_STIR\_INTID\_Pos}{NVIC\_STIR\_INTID\_Pos}\hspace{0.1cm}{\footnotesize\ttfamily [5/8]}}
{\footnotesize\ttfamily \label{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8} 
\#define NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos~0U}

STIR\+: INTLINESNUM Position \Hypertarget{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}\index{Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}!NVIC\_STIR\_INTID\_Pos@{NVIC\_STIR\_INTID\_Pos}}
\index{NVIC\_STIR\_INTID\_Pos@{NVIC\_STIR\_INTID\_Pos}!Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}}
\doxysubsubsubsubsection{\texorpdfstring{NVIC\_STIR\_INTID\_Pos}{NVIC\_STIR\_INTID\_Pos}\hspace{0.1cm}{\footnotesize\ttfamily [6/8]}}
{\footnotesize\ttfamily \label{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8} 
\#define NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos~0U}

STIR\+: INTLINESNUM Position \Hypertarget{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}\index{Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}!NVIC\_STIR\_INTID\_Pos@{NVIC\_STIR\_INTID\_Pos}}
\index{NVIC\_STIR\_INTID\_Pos@{NVIC\_STIR\_INTID\_Pos}!Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}}
\doxysubsubsubsubsection{\texorpdfstring{NVIC\_STIR\_INTID\_Pos}{NVIC\_STIR\_INTID\_Pos}\hspace{0.1cm}{\footnotesize\ttfamily [7/8]}}
{\footnotesize\ttfamily \label{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8} 
\#define NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos~0U}

STIR\+: INTLINESNUM Position \Hypertarget{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8}\index{Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}!NVIC\_STIR\_INTID\_Pos@{NVIC\_STIR\_INTID\_Pos}}
\index{NVIC\_STIR\_INTID\_Pos@{NVIC\_STIR\_INTID\_Pos}!Nested Vectored Interrupt Controller (NVIC)@{Nested Vectored Interrupt Controller (NVIC)}}
\doxysubsubsubsubsection{\texorpdfstring{NVIC\_STIR\_INTID\_Pos}{NVIC\_STIR\_INTID\_Pos}\hspace{0.1cm}{\footnotesize\ttfamily [8/8]}}
{\footnotesize\ttfamily \label{group___c_m_s_i_s___c_o_r_e_ga9eebe495e2e48d302211108837a2b3e8} 
\#define NVIC\+\_\+\+STIR\+\_\+\+INTID\+\_\+\+Pos~0U}

STIR\+: INTLINESNUM Position \input{group___c_m_s_i_s___s_c_b}
